1. Field of Invention
The present invention relates to a semiconductor memory and in particular a combinational nonvolatile memory utilizing both one-transistor Flash and two-transistor EEPROM memory made from the same technology and providing simultaneous read and write operations.
2. Description of Related Art
Many electronic applications require writing data into the memory while at the same time reading program code from the memory, and many systems utilize both block-erasable Flash memory and byte-erasable EEPROM to perform this dual function. The block-erasable Flash memory stores program codes having less frequent update rates, and the byte-erasable EEPROM stores the data and parameters with a high update frequency rate with self-timed Write control. This allows data to be written to the EEPROM while the program code is read from the Flash memory simultaneously.
Since the data and parameters stored in the system needs to be frequently updated in small units of a byte or a page, the data is preferred to be stored in a byte-erasable EEPROM. Using an EEPROM to store both the program code and data is not very cost effective because of the large cell size of the EEPROM. Using Flash memory to store both the program code and data is not easy because Flash memory lacks the byte-level data alterability as provided in an EEPROM. Flash memory erases a large block size of data, 64K×8, at one time because of the Flash memory array architecture. It is very difficult to perform byte-level data update with this block erase feature; therefore, there is a software solution that is proposed to emulate the byte-erasable EEPROM with the architecture of block-erasable Flash memory. As a result, a highly complex software technique is required which causes drastic system performance degradation, and sometimes may cause reliability problem.
The integration of a Flash and EEPROM memory in a single memory chip is highly desirable for reducing cost, device footprint, and power consumptions while providing superior performance; however, since the cell structure and process technology is different between Flash and EEPROM memories, combining these two memories into one chip requires very complex process flow, which is not cost effective.
In U.S. Pat. No. 6,370,081 (Sakui, et al.) a nonvolatile memory cell is directed to having a memory cell and two select transistors sandwiching the memory cell. One block of memory nonvolatile memory cells has one control gate line. The nonvolatile memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After the data is sensed and stored in the sense amplifiers a page erase is performed. The data from the sense amplifiers are programmed in the memory cells of one page. Data in the sense amplifiers maybe changed in the sense amplifiers prior to the reprogramming to allow byte or page data programming.
U.S. Pat. No. 6,400,604 (Noda) is directed to a nonvolatile semiconductor memory device having a data reprogram mode. The memory has a memory cell array, a page buffer for storing one page data to be programmed to memory cells, which are selected in accordance with a page address signal. The memory further has an internal column address generating circuit for generating column addresses of the one page with inputting the page address signal in order to transfer the one data stored in the page buffer to the memory cells, a column decoder receiving the column addresses from the internal column address generating circuit, and a control circuit having a data reprogram mode. The data reprogram mode erases one page data stored in the memory cells which are selected in accordance with the page address signal and programs the one page data stored in the page buffer to the memory cells which are selected.
U.S. Pat. No. 6,307,781 (Shum) is directed to providing a two transistor cell NOR architecture flash memory. The floating gate transistor is placed between the selection transistor and an associated bit line as shown in FIGS. 2a-c. The flash memory is deposited within a triple well and operates according to a Fowler-Nordheim tunnel mechanism. Programming of memory cells involves tunneling of carriers through gate oxide from a channel region to a floating gate rather than tunneling from a drain or source region to the floating gate.
U.S. Pat. No. 6,212,102 (Georgakos, et al.) is directed to illustrating an EEPROM with two-transistor memory cells with source-side selection. The voltage required to program a memory cell is delivered via a source line.
U.S. Pat. No. 6,266,274 (Pockrandt, et al.) is directed to a non-volatile two-transistor memory cell which has an N-channel selection transistor and an N-channel memory transistor. The drive circuitry for the cell includes a P-channel transfer transistor. A transfer channel is connected to a row line leading to the memory cell.
U.S. Pat. No. 6,174,759 (Verhaar, et al.) directed to an EEPROM cell that is provided with such a high-voltage transistor as a selection transistor similar to that described in FIGS. 2a-c. Apart from the n-well implantation, high-voltage transistors of the p-channel are largely manufactured by means of the same process steps as the p-channel transistors in the logic, so that the number of process steps remains limited.
U.S. Pat. No. 6,326,661 (Dormans, et al) is directed to a floating gate memory cell having a large capacitive coupling between the control gate and the floating gate. The control gate is capacitive coupled to the substantially flat surface portion of the floating gate and to at least the side-wall portions of the floating gate facing the source and the drain, and ends above the substantially flat surface portion of the select gate. These measures provide a semiconductor device having a large capacitive coupling between the control gate and the floating gate of the memory cell thus increasing the coupling ratio.
U.S. Pat. No. 5,748,538 (Lee, et al.), assigned to the same assignee as the present invention, describes an OR-plane memory cell array for flash memory with bit-based write capability. The memory cell array of a flash electrically erasable programmable read only memory (EEPROM) includes nonvolatile memory cells arranged in rows and columns. The sources of nonvolatile memory cells in the same memory block are connected to a main source line through a control gate. Similarly, the drains of the nonvolatile memory cells of the same memory block are connected to a main bit line. The separate source and drains in the column direction are designed for a bit-based write capability. Writing, such as erasing or programming, of a selected nonvolatile memory cell uses the Fowler-Nordheim tunneling method and can be accomplished due to the programming or erase inhibit voltage that is applied to non-selected nonvolatile memory cells.